Asia-Pacific Workshop on Fundamental and application of Advanced Semiconductor Devices, pp.11 - 16
Abstract
A patterning technique to define nanoscale poly-Si lines is developed using sidewall structure. In this experiment, sidewall patterning technique makes it possible to realize 30nm, 50nm and 80nm poly-Si lines accurately, uniformly, and reproducibly. We have compared this technique with e-beam lithography. It is expected that the sidewall patterning technique can be applied to nanoscale MOSFET fabrication.