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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Operation and Data Mapping for CGRAs with Multi-bank Memory

Cited 2 times inthomson ciCited 2 times inthomson ci
Title
Operation and Data Mapping for CGRAs with Multi-bank Memory
Author
Kim, YongjooLee, JongeunShrivastava, AviralPaek, Yunheung
Keywords
Application mapping; Coarse grained reconfigurable architecture; Coarse-grain reconfigurable architectures; Data mappings; High-power; Local memories; Mapping applications; Memory banks; Multimedia benchmarks; Power-efficiency; Share memory
Issue Date
201004
Publisher
ASSOC COMPUTING MACHINERY
Citation
ACM SIGPLAN NOTICES, v.45, no.4, pp.17 - 25
Abstract
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multi-bank local memory, and a row of PEs share memory access. In order for each row of the PEs to access any memory bank, there is a hardware arbiter between the memory requests generated by the PEs and the banks of the local memory. However, a fundamental restriction remains that a bank cannot be accessed by two different PEs at the same time. We propose to meet this challenge by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts. Our experimental results on kernels from multimedia benchmarks demonstrate that our local memory-aware compilation approach can generate mappings that are up to 40% better in performance (17.3% on average) compared to a memory-unaware scheduler.
URI
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DOI
http://dx.doi.org/10.1145/1755951.1755892
ISSN
0362-1340
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