IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, no.1, pp.293 - 300
Abstract
A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge2Sb2Te5) into 0.18-mum CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30degreesC.