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Lee, Jongeun
Intelligent Computing and Codesign Lab.
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Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces

Author(s)
Sim, HyeonukRahman, AtulLee, Jongeun
Issued Date
2016-08
DOI
10.1109/TVLSI.2016.2520491
URI
https://scholarworks.unist.ac.kr/handle/201301/20687
Fulltext
http://ieeexplore.ieee.org/document/7401111/
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.8, pp.2799 - 2802
Abstract
Most existing solutions to pipelining nested loops are developed for general purpose processors, and may not work efficiently for field-programmable gate arrays due to loop control overhead. This is especially true when the nested loops have nonrectangular iteration spaces (IS). Thus we propose a novel method that can transform triangular IS-the most frequently found type of nonrectangular IS-into rectangular ones, so that other loop transformations can be effectively applied and the overall performance of nested loops can be maximized. Our evaluation results using the state-of-the-art Vivado high-level synthesis tool demonstrate that our technique can improve the performance of nested loops with nonrectangular IS significantly.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
1063-8210
Keyword (Author)
Field-programmable gate array (FPGA)high level synthesisloop coalescingloop flatteningnested looptriangular iteration space

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