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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 2802 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 2799 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 24 | - |
dc.contributor.author | Sim, Hyeonuk | - |
dc.contributor.author | Rahman, Atul | - |
dc.contributor.author | Lee, Jongeun | - |
dc.date.accessioned | 2023-12-21T23:16:59Z | - |
dc.date.available | 2023-12-21T23:16:59Z | - |
dc.date.created | 2016-11-04 | - |
dc.date.issued | 2016-08 | - |
dc.description.abstract | Most existing solutions to pipelining nested loops are developed for general purpose processors, and may not work efficiently for field-programmable gate arrays due to loop control overhead. This is especially true when the nested loops have nonrectangular iteration spaces (IS). Thus we propose a novel method that can transform triangular IS-the most frequently found type of nonrectangular IS-into rectangular ones, so that other loop transformations can be effectively applied and the overall performance of nested loops can be maximized. Our evaluation results using the state-of-the-art Vivado high-level synthesis tool demonstrate that our technique can improve the performance of nested loops with nonrectangular IS significantly. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.8, pp.2799 - 2802 | - |
dc.identifier.doi | 10.1109/TVLSI.2016.2520491 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.scopusid | 2-s2.0-84958662217 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/20687 | - |
dc.identifier.url | http://ieeexplore.ieee.org/document/7401111/ | - |
dc.identifier.wosid | 000384916500019 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Computer Science; Engineering | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Field-programmable gate array (FPGA) | - |
dc.subject.keywordAuthor | high level synthesis | - |
dc.subject.keywordAuthor | loop coalescing | - |
dc.subject.keywordAuthor | loop flattening | - |
dc.subject.keywordAuthor | nested loop | - |
dc.subject.keywordAuthor | triangular iteration space | - |
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