Novel five-state latch using double-peak negative differential resistance and standard ternary inverter

Abstract

We propose complement double-peak negative differential resistance (NDR) devices with ultrahigh peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with conventional CMOS and its compact five-state latch circuit by introducing standard ternary inverter (STI). At the "high"-state of STI, n-type NDR device (tunnel diode with nMOS) has 1st NDR characteristics with 1st peak and valley by band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT), whereas p-type NDR device (tunnel diode with pMOS) has second NDR characteristics from the suppression of diode current by off-state MOSFET. The "intermediate"-state of STI permits double-peak NDR device to operate five-state latch with only four transistors, which has 33% area reduction compared with that of binary inverter and 57% bit-density reduction compared with binary latch.