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Issue Date	Title	Author(s)	Type	View	Altmetrics
2016-07	Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC	Kim, Seung Won; Kang, Seokhyeong; Han, Ki Jin, et al	ARTICLE	1055	Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC
2016-07	Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization	Kim, Sangmin; Kang, Seokhyeong; Shin, Youngsoo	ARTICLE	823	Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization
2016-03	Wakeup scheduling and its buffered tree synthesis for power gating circuits	Kim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong, et al	ARTICLE	917	Wakeup scheduling and its buffered tree synthesis for power gating circuits
2015-09	An Improved Methodology for Resilient Design Implementation	Kahng, Andrew B.; Kang, Seokhyeong; Li, Jiajia, et al	ARTICLE	924	An Improved Methodology for Resilient Design Implementation
2013-10	Enhancing the Efficiency of Energy-Constrained DVFS Designs	Kahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh, et al	ARTICLE	1014	Enhancing the Efficiency of Energy-Constrained DVFS Designs
2013-08	Many-Core Token-Based Adaptive Power Gating	Kahng, Andrew B.; Kang, Seokhyeong; Rosing, Tajana Simunic, et al	ARTICLE	997	Many-Core Token-Based Adaptive Power Gating
2012-03	Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors	Kahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh, et al	ARTICLE	1031	Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

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