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Kang, Seokhyeong (강석형) (2014-08~2018-03)

Department
전기전자컴퓨터공학부
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Issue DateTitleAuthor(s)TypeViewAltmetrics
2016-07Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D ICKim, Seung Won; Kang, Seokhyeong; Han, Ki Jin, et alARTICLE737 Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC
2016-07Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimizationKim, Sangmin; Kang, Seokhyeong; Shin, YoungsooARTICLE529 Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization
2016-03Wakeup scheduling and its buffered tree synthesis for power gating circuitsKim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong, et alARTICLE563 Wakeup scheduling and its buffered tree synthesis for power gating circuits
2015-09An Improved Methodology for Resilient Design ImplementationKahng, Andrew B.; Kang, Seokhyeong; Li, Jiajia, et alARTICLE598 An Improved Methodology for Resilient Design Implementation
2013-10Enhancing the Efficiency of Energy-Constrained DVFS DesignsKahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh, et alARTICLE639 Enhancing the Efficiency of Energy-Constrained DVFS Designs
2013-08Many-Core Token-Based Adaptive Power GatingKahng, Andrew B.; Kang, Seokhyeong; Rosing, Tajana Simunic, et alARTICLE627 Many-Core Token-Based Adaptive Power Gating
2012-03Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient ProcessorsKahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh, et alARTICLE608 Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

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