Indium Tin Oxide Vertical Channel Transistors for Scaled 4F2 2T0C Gain Cell Memory With Etched Sidewall Cleaning

Abstract

2T0C gain cell memory based on amorphous oxide semiconductor vertical channel transistors (VCTs) has emerged as a promising high-density embedded dynamic access memory solution for memory-centric computing systems, monolithically integrated atop silicon logic. This capacitor-less memory offers long retention time and a compact 4F(2) cell footprint, enabling low-power and area-efficient integration above logic circuits. In this work, amorphous indium tin oxide VCTs and 2T0C gain cells with hole diameters scaled down to 150 nm were fabricated. However, scaling the hole diameter caused residual etch by-products to accumulate along the channel sidewalls, degrading the subthreshold swing and on-state current. To mitigate this issue, a sidewall cleaning process was introduced to effectively remove the residues. The treatment improved the VCT on-state current by over three orders of magnitude and enabled stable single- and two-bit memory operation with retention time exceeding 160 s.