Bias-Temperature Instability Characteristics of High-k Metal Gate Ternary CMOS Technology

Abstract

As CMOS technology approaches its power scaling limits, multi-valued logic has emerged as a promising alternative to improve energy efficiency and integration density. Among them, Ternary CMOS (T-CMOS) offers significant advantages; however, its practical deployment critically depends on the long-term reliability of the underlying devices, particularly under bias temperature instability (BTI). Due to reduced noise margins and the presence of intermediate logic states, BTI-induced threshold voltage degradation poses a more severe reliability challenge in T-CMOS than in conventional binary CMOS. In this work, the BTI characteristics of high-k metal gate (HKMG) MOSFETs fabricated for Ternary CMOS operation are systematically investigated. The physical components of BTI degradation are defined and analyzed, including interface trap generation (ΔNIT), pre-existing charge trapping (ΔNHT, ΔNET), and oxide-bulk trap generation(ΔNOT). An experimental extraction methodology is established based on C–V calibration and midgap- based stress voltage selection to minimize ΔVOT contributions. NBTI and PBTI behaviors are evaluated over a several conditions of gate voltage, temperature, and stress time conditions. The results show that both ternary and binary CMOS devices exhibit similar BTI degradation kinetics, indicating identical underlying physical mechanisms. However, ternary devices demonstrate distinct degradation characteristics arising from differences in pre-existing trap conditions rather than mechanism changes. Flicker noise measurements reveal an increased density of pre-existing traps in ternary CMOS devices, which significantly affect BTI behavior by enhancing charge trapping during stress and modifying voltage and time acceleration characteristics. While NBTI exhibits an increased ΔVIT due to enhanced interface damage induced by increased halo implant, a trapping-dominant degradation regime is observed in PBTI, leading to reduced voltage acceleration factors and time exponents without introducing new degradation mechanisms. Based on experimentally extracted BTI parameters and initial trap densities, using empirical model lifetime prediction framework is implemented to estimate the 10-year threshold voltage shift at nominal operating voltage. The results provide a quantitative assessment of long-term reliability for ternary CMOS devices under realistic use conditions. This study demonstrates that increasing in halo implantation does not change the physical mechanisms of BTI components and provides a quantitative analysis of their impact on the reliability of ternary CMOS devices.