The premium smartphone market is rapidly shifting toward On-Device AI implementation. Consequently, integrating high-performance NPU (Neural Processing Unit) and GPU (Graphics Processing Unit) into SoC alongside CPU (Central Processing Unit) has become a dominant technological trend. However, the inclusion of these high-performance processors significantly increases the total power consumption of SoC systems, posing critical challenges such as reduced battery life and thermal issues. To address these issues, this paper proposes a novel Dual-Mode Hybrid Switched-Capacitor (SC) Buck Converter designed for stable and highly efficient power delivery to SoCs. By employing an Inductor-middle topology, the proposed architecture simultaneously achieves the reduced inductor current characteristic of Inductor-first structures and the wide conversion ratio capability of Inductor- last structures. A mode-transition circuit further optimizes efficiency across different operating modes. Additionally, a calibration circuit and an interleaved architecture are utilized to maintain stable flying capacitor voltages, successfully supporting the wide output voltage range of 0.4-to-1.5 V required by the SoC. The entire system is implemented in TSMC 180 nm CMOS technology, occupying an active area of 1.3 mm². Simulation results confirm stable operation with small ripple below 12 mV and peak efficiency above 95.7%, demonstrating its suitability for power- and ripple-sensitive logic rails across the 0.4-to- 1.5 V range.
Publisher
Ulsan National Institute of Science and Technology