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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | KO | - |
| dc.citation.conferencePlace | 제주 | - |
| dc.citation.title | 8th International Conference on Advanced Electromaterials (ICAE 2025) | - |
| dc.contributor.author | Park, Kibog | - |
| dc.contributor.author | Jo, Jaehyeong | - |
| dc.contributor.author | Kim, Jiwan | - |
| dc.contributor.author | Park, Hyunjae | - |
| dc.contributor.author | Hyun, Eunseok | - |
| dc.contributor.author | Park, Jungjae | - |
| dc.date.accessioned | 2026-01-08T15:41:22Z | - |
| dc.date.available | 2026-01-08T15:41:22Z | - |
| dc.date.created | 2026-01-06 | - |
| dc.date.issued | 2025-11-25 | - |
| dc.description.abstract | The superconducting qubit system is currently the leading platform in the race of building a commer-cial quantum computer. Due to the relatively large size (several tens of micrometers) of supercon-ducting devices, the scalability of superconducting qubit system in a 2D plane is strongly limited. Hence, it is quite challenging to pack superconducting qubits over 100 with a planar architecture un-less a chip is substantially oversized. One viable strategy to overcome this limitation of 2D planar architecture is so-called multi-tier architecture where a control chip harnessing the circuitry for driv-ing and reading out superconducting qubits(feedlines, resonators) is fabricated separately and it is stacked vertically with a qubit chip in which the space occupied previously by the control elements are now freed up. The key technological elements of multi-tier architecture are superconducting bump flip-chip bonding and through-Si-via(TSV) interconnect line [1]. The superconducting bump flip-chip bonding is for connecting a qubit chip and a control chip electrically while keeping the pre-determined spacing between the two chips. The TSV interconnect line enables inserting another layer between qubit and control chips, called typically an interposer, which provides more flexibility in routing the signal lines of control chip and also make any lossy dielectric materials of control chip further apart from the qubit chip. In this talk, the overview for the 3D integration processes to realize the multi-tier architecture will be given, including the domestic and international status of adopting it to the actual processor fabrication [2]. Additionally, our recent works of fabricating a two-tier super-conducting quantum processor by stacking a twenty-qubit transmon chip on top of a control chip will be introduced in terms of the fabrication procedures and operational characteristics of processor. References [1] D. Rosenberg et al., npj Quantum Information 42 (2017) [2] S. Kosen et al., Quantum Science and Technology 7 035018 (2022) |
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| dc.identifier.bibliographicCitation | 8th International Conference on Advanced Electromaterials (ICAE 2025) | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/90039 | - |
| dc.publisher | The Korean Institute OF Electrical and Electronic Material Engineers | - |
| dc.title | 3D-Integrated Multi-Tier Architecture for Scaling up Superconducting Quantum Processor | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2025-11-25 | - |
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