Compact Model-Based Ternary SRAM Design and Stability Analysis

Abstract

This work presents a tunneling-based ternary CMOS (T-CMOS) technology to enable off-state working for always-on mobile and edge applications. While previous research has focused on scaling down VDD to reduce both switching and leakage power, such scaling can degrade memory stability due to increased process variations. Although various SRAM cell designs (e.g., 8T, 9T, and 10T) have been proposed to improve stability, they often bring increased system complexity and power consumption. To address this issue, we propose T-CMOS, tunneling-based ternary logic device capable of processing three logic states with an area comparable to conventional 6T SRAM, which operates stable under low VDD (< 1 V). A compact model of band-to-band tunneling current (IBTBT ), valid in sub-1 V operation, is developed, and the parameter tendency on doping concentration and VDD are analytically derived. Parasitic capacitances are also modeled to support accurate AC and transient analysis, enabling power and performance prediction under various VDDs. Using this model, we design and demonstrate an ultra- low-power 6T ternary SRAM (T-SRAM) cell. The cell employs two cross-coupled T-CMOS devices to form a ternary latch (T-Latch), enabling storage of three distinct logic states. To address read delay under off-state conditions, a half-VDD precharge read scheme is proposed. In this mode, the dominant factor in read latency is the recovery time of Q and QB nodes, influenced by charge-sharing effects. The proposed read strategy improves read speed while maintaining ultra-low power operation. Since T-SRAM operates in a highly energy-constrained regime, the effects of bitline capacitance and layout- induced RC parasitics become critical during transient operation. Therefore, we evaluate the cell’s stability and design margin using dynamic noise margin (DNM) and static noise margin (SNM) analysis that incorporates full parasitic modeling. Finally, we demonstrate a high-density and energy-efficient ternary content-addressable memory (TCAM) based on T-CMOS. The proposed TCAM cell reduces the transistor count from 16 to 6 and eliminates redundant search paths by sharing wordline and search transistors. Moreover, it supports hybrid binary-ternary operations by adapting to different VDD levels. The power-scalable T-CMOS architecture presented in this work is well-suited for extremely energy- efficient, always-on applications such as AIoT, wearable electronics, and biomedical devices.