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- Yoon, Heein
- Advanced Circuits and Electronics Lab.
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A 6.2b-ENOB 2.5GS/s Flash-and-VCO Based Subranging ADC Using a Residue Shifting Technique
- Author(s)
- Kim, Sungjin, Lee, Jeonghyun, Cho, Yoonse, Kim, Jintae, Choi, Jeahyouk, Yoon, Heein
- Issued Date
- 2025-06
- Citation
- IEEE SOLID-STATE CIRCUITS LETTERS, v.8, pp.177 - 180
- Abstract
- This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the KVCO, thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.
- Publisher
- IEEE
- ISSN
- 2573-9603
- Keyword (Author)
- Analog-to-digital converter (ADC), pipeline ADC, voltage-controlled oscillator (VCO)
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