Multi-Tier Architecture for Large-Scale Superconducting Quantum Processor

Abstract

The superconducting qubit system is currently the leading platform in the race of building a commercial quantum computer. Compared with the conventional semiconductor devices, superconducting devices are pretty large, several tens of micrometers in size. Hence, the scalability of superconducting qubit system in a 2D plane is strongly limited so that it will be quite challenging to pack superconducting qubits over 100 with a planar architecture unless a chip is substantially oversized. One viable strategy to overcome this limitation of 2D planar architecture is so-called multi-tier architecture where the circuitry for driving and reading out superconducting qubits(feedlines, resonators) is fabricated on a separate chip(control chip) and it is stacked vertically with a qubit chip in which the space occupied previously by the control elements are now freed up. The key technological elements of multi-tier architecture are superconducting bump flip-chip bonding and through-Si-via(TSV) interconnect line [1]. The superconducting bump flip-chip bonding is for connecting a qubit chip and a control chip electrically while keeping the pre-determined spacing between the two chips. The TSV interconnect line enables inserting another layer between qubit and control chips, called typically an interposer, which provides more flexibility in routing the signal lines of control chip to the qubit chip. In this talk, the overview for the multi-tier architecture of superconducting quantum processor will be given, including the domestic and international status of adopting it to the actual processor fabrication [2]. Additionally, our recent works of fabricating a two-tier superconducting quantum processor by stacking a five-qubit transmon chip on top of a control chip will be introduced in terms of the fabrication procedures and operational characteristics of qubits.

[1] D. Rosenberg et al., “3D integrated superconducting qubits”, npj Quantum Information 42 (2017) [2] S. Kosen et al., “Building blocks of a flip-chip integrated superconducting quantum processor”, Quantum Science and Technology 7 035018 (2022)