Competition between Bipolar Conduction Modes in Extrinsically p-Doped MoS2: Interaction with Gate Dielectric Matters

Abstract

With reduced dimensionality and a high surface area-to-volume ratio, two-dimensional (2D) semiconductors exhibit intriguing electronic properties that are exceptionally sensitive to surrounding environments, including directly interfacing gate dielectrics. These influences are tightly correlated to their inherent behavior, making it critical to examine when extrinsic charge carriers are intentionally introduced to the channel for complementary functionality. This study explores the physical origin of the competitive transition between intrinsic and extrinsic charge carrier conduction in extrinsically p-doped MoS2, highlighting the central role of interactions of the channel with amorphous gate dielectrics. By providing a pristine interface to the channel and controlling the degree of such interaction using hexagonal boron nitride (h-BN) spacers of different thicknesses, we determined three distinctive interaction modes: noncontact, proximity, and direct-contact. In the direct-contact mode without an h-BN spacer, charge transfer and orbital mixing induce ambipolar conduction in few-layer p-doped MoS2, showing an unexpected gate-dependent crossover between coexisting extrinsic and intrinsic conduction. Kelvin probe force microscopy and Raman spectroscopy confirm n-type doping in the channel through dielectric interactions, further supported by first-principles calculations identifying unpassivated silicon dangling bonds on the SiO2 surface as the origin of n-doping. On the contrary, depending on the thickness of the h-BN spacers, the noncontact mode maintains degenerate p-type conduction in the transfer curve, while the proximity mode enables gate-responsive p-type conduction, emphasizing the significant role of dielectric interactions in modulating charge transport. These findings underscore the importance of dielectric engineering in optimizing 2D semiconductor devices, particularly for improving the p-type transistor performance.