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Jeong, Hu Young
UCRF Electron Microscopy group
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dc.citation.startPage 2314274 -
dc.citation.title ADVANCED MATERIALS -
dc.contributor.author Kim, Yeon Ho -
dc.contributor.author Jiang, Wei -
dc.contributor.author Lee, Donghun -
dc.contributor.author Moon, Donghoon -
dc.contributor.author Choi, Hyun-Young -
dc.contributor.author Shin, June-Chul -
dc.contributor.author Jeong, Yeonsu -
dc.contributor.author Kim, Jong Chan -
dc.contributor.author Lee, Jaeho -
dc.contributor.author Huh, Woong -
dc.contributor.author Han, Chang Yong -
dc.contributor.author So, Jae-Pil -
dc.contributor.author Kim, Tae Soo -
dc.contributor.author Kim, Seong Been -
dc.contributor.author Koo, Hyun Cheol -
dc.contributor.author Wang, Gunuk -
dc.contributor.author Kang, Kibum -
dc.contributor.author Park, Hong-Gyu -
dc.contributor.author Jeong, Hu Young -
dc.contributor.author Im, Seongil -
dc.contributor.author Lee, Gwan-Hyoung -
dc.contributor.author Low, Tony -
dc.contributor.author Lee, Chul-Ho -
dc.date.accessioned 2024-05-28T15:35:10Z -
dc.date.available 2024-05-28T15:35:10Z -
dc.date.created 2024-05-23 -
dc.date.issued 2024-04 -
dc.description.abstract A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of approximate to 60 mV dec(-1) and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (E-F) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that E-F depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics. -
dc.identifier.bibliographicCitation ADVANCED MATERIALS, pp.2314274 -
dc.identifier.doi 10.1002/adma.202314274 -
dc.identifier.issn 0935-9648 -
dc.identifier.scopusid 2-s2.0-85191810760 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/82797 -
dc.identifier.wosid 001216647900001 -
dc.language 영어 -
dc.publisher WILEY-V C H VERLAG GMBH -
dc.title Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit -
dc.type Article -
dc.description.isOpenAccess TRUE -
dc.relation.journalWebOfScienceCategory Chemistry, Multidisciplinary; Chemistry, Physical; Nanoscience & Nanotechnology; Materials Science, Multidisciplinary; Physics, Applied; Physics, Condensed Matter -
dc.relation.journalResearchArea Chemistry; Science & Technology - Other Topics; Materials Science; Physics -
dc.type.docType Article; Early Access -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor MoS2 -
dc.subject.keywordAuthor 2D semiconductors -
dc.subject.keywordAuthor Fermi-level pinning -
dc.subject.keywordAuthor low-power electronics -
dc.subject.keywordAuthor metal-semiconductor field-effect transistors -

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