Development of Power Hardware-in-the-Loop Simulation Test-bed to Verify LVDC Grid Stability Using Offline Damping Impedance Design

Abstract

In this paper, a Damping Impedance Method (DIM)-applied Power Hardware-in-the-Loop Simulation (HILS) test-bed is proposed to test the stability of a Low Voltage DC (LVDC) grid composed of multiple converters. The impedance interaction between the source-side system and load-side system which consists of the LVDC grid is analyzed by the Extra Element Theorem (EET). Furthermore, the stability of the LVDC grid is assessed by using the Opposing Argument Criterion (OAC). Using those analyses, the Power HILS test-bed is implemented using the DIM. This approach leverages the CPL characteristics of the load-side system to propose an offline design method for the damping impedance used in the DIM, which can reduce implementation complexity and can obtain an accurate Power HILS test-bed. Finally, the accuracy and effectiveness of the proposed Power HILS test-bed are verified using a 500-W Dual-Active-Bridge (DAB) converter.