3D Integration for Large-Scale Superconducting Quantum Processor

Abstract

In recent years, there have been many eye-catching progresses in the quantum computing field, marching toward the true demonstration of so-called quantum supremacy[1]. The leading platform at the present stage is the superconducting qubit system on which the main tech companies including Google, IBM, and D-Wave, are working extensively. Compared with the conventional semiconductor devices, superconducting devices are pretty large, several tens of micrometers in size. Hence, the scalability of superconducting qubit system in a 2D plane is strongly limited so that it will be quite challenging to pack superconducting qubits over 100 with a planar architecture unless a very large chip is used. One straightforward way to overcome this limitation in scaling is to construct a superconducting qubit system in the 3D fashion where the circuitry for driving and reading out superconducting qubits(feedlines, resonators) is fabricated on a separate chip(control chip) and it is stacked vertically(3D integration) with a qubit chip. With this approach, we can free up the space in the planar-architecture qubit chip which is occupied by the drive/read-out circuitry and put additional qubits there, leading eventually to the increase of scalability. The key technological elements of 3D integration is superconducting bump flip-chip bonding and through-Si-via(TSV) interconnect line. The superconducting bump flip-chip bonding is for connecting a qubit chip and a control chip electrically while keeping the pre-determined spacing between the two chips. The TSV interconnect line enables inserting another layer between qubit and control chips, called typically an interposer, which provides more flexibility in routing the signal lines of control chip and also separate the qubit and control chips further to help suppressing the stray electromagnetic influences from the control chip onto the qubits. In this talk, the overview for the 3D integration of superconducting quantum processor will be given, including the domestic and international status of developing its core and associated technologies. Additionally, our recent achievements in fabricating a two-tier superconducting quantum processor constructed by stacking a five-qubit superconducting transmon chip and a control chip will be introduced.