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Baek, Woongki
Intelligent System Software Lab.
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dc.citation.conferencePlace US -
dc.citation.title IEEE International Conference on Computer Design -
dc.contributor.author Kim, Kyu Yeun -
dc.contributor.author Baek, Woongki -
dc.date.accessioned 2024-02-01T01:11:56Z -
dc.date.available 2024-02-01T01:11:56Z -
dc.date.created 2018-12-16 -
dc.date.issued 2018-10-07 -
dc.description.abstract GPGPUs with heterogeneous memory have surfaced as a promising solution to improve the programmability and flexibility of GPGPU computing. Despite the extensive prior works, relatively little work has been done to investigate holistic system software support for heterogeneity-aware memory management. To bridge this gap, we propose bandwidth- and latencyaware page placement (BLPP) for GPGPUs with heterogeneous memory. BLPP dynamically places pages across the heterogeneous memory nodes by preserving the optimal allocation ratio computed based on their performance characteristics. Our experimental results show that BLPP considerably outperforms the state-of-the-art technique and performs similarly to the staticbest version, which requires extensive offline profiling. -
dc.identifier.bibliographicCitation IEEE International Conference on Computer Design -
dc.identifier.doi 10.1109/ICCD.2018.00061 -
dc.identifier.scopusid 2-s2.0-85062229120 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/80841 -
dc.identifier.url https://ieeexplore.ieee.org/document/8615711 -
dc.language 영어 -
dc.publisher IEEE -
dc.title BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement -
dc.type Conference Paper -
dc.date.conferenceDate 2018-10-07 -

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