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- Jeong, Changwook
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.conferencePlace | Portland, OR | - |
| dc.citation.title | 2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC) | - |
| dc.contributor.author | Min, Jeong Guk | - |
| dc.contributor.author | Jeong, Changwook | - |
| dc.contributor.author | Kwon, Uihui | - |
| dc.contributor.author | Kim, Dae Sin | - |
| dc.contributor.author | Kim, Suhyun | - |
| dc.contributor.author | Kim, Ilryoung | - |
| dc.contributor.author | Yang, Joon-Sung | - |
| dc.date.accessioned | 2024-02-01T01:10:50Z | - |
| dc.date.available | 2024-02-01T01:10:50Z | - |
| dc.date.created | 2022-04-11 | - |
| dc.date.issued | 2018-10-14 | - |
| dc.description.abstract | The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moiré fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures. | - |
| dc.identifier.bibliographicCitation | 2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC) | - |
| dc.identifier.doi | 10.1109/nmdc.2018.8605736 | - |
| dc.identifier.scopusid | 2-s2.0-85061784248 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/80787 | - |
| dc.publisher | IEEE | - |
| dc.title | The Impact of Dislocation on Bulk -Si FinFET Technologies: Physical Modeling of Strain Relaxation and Enhancement by Dislocation | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2018-10-14 | - |
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