dc.citation.endPage |
U8 |
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dc.citation.number |
5 |
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dc.citation.startPage |
239 |
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dc.citation.title |
ELECTRONICS LETTERS |
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dc.citation.volume |
45 |
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dc.contributor.author |
Choi, Jaehyouk |
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dc.contributor.author |
Park, J. |
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dc.contributor.author |
Kim, W. |
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dc.contributor.author |
Lim, K. |
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dc.contributor.author |
Laskar, J. |
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dc.date.accessioned |
2023-12-22T08:09:50Z |
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dc.date.available |
2023-12-22T08:09:50Z |
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dc.date.created |
2014-10-30 |
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dc.date.issued |
2009-02 |
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dc.description.abstract |
A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8pF using an on-chip capacitor of 7.95pF with current consumption of 100A. An integer-N PLL with a channel space of 1MHz was fabricated with a 0.18m CMOS technology to employ the proposed capacitor multiplier. |
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dc.identifier.bibliographicCitation |
ELECTRONICS LETTERS, v.45, no.5, pp.239 - U8 |
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dc.identifier.doi |
10.1049/el:20092874 |
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dc.identifier.issn |
0013-5194 |
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dc.identifier.scopusid |
2-s2.0-61349169647 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/8071 |
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dc.identifier.url |
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=61349169647 |
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dc.identifier.wosid |
000263785600001 |
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dc.language |
영어 |
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dc.publisher |
INST ENGINEERING TECHNOLOGY-IET |
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dc.title |
High multiplication factor capacitor multiplier for an on-chip PLL loop filter |
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dc.type |
Article |
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dc.description.journalRegisteredClass |
scopus |
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