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Yoon, Heein
Advanced Circuits and Electronics Lab.
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dc.citation.conferencePlace US -
dc.citation.conferencePlace San Francisco -
dc.citation.endPage 260 -
dc.citation.startPage 258 -
dc.citation.title IEEE International Solid-State Circuits Conference - Kim, Juyeop - Yoon, Heein - Lim, Younghyun - Lee, Yongsun - Cho, Yoonseo - Seong, Taeho - Choi, Jaehyouk - 2024-02-01T00:38:31Z - 2024-02-01T00:38:31Z - 2019-04-29 - 2019-02-17 -
dc.description.abstract The generation of mm-wave (mmW) signals that have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated PN (IPN) [1]. To satisfy such stringent noise requirements, the rms jitter of mmW-band signals must be reduced to sub-100fs. Recently, a charge-pump (CP) PLL in [1] achieved a very low rms jitter of less than 60fs at 14GHz. However, to suppress the in-band PN of PLL building blocks, that design used a reference clock that had an impractically high frequency, f-{{REF}}, of 500MHz. To avoid the use of such a high f-{{REF}} while minimizing in-band PN, sub-sampling PLLs (SSPLLs) are seen as a promising solution. However, conventional SSPLLs are not suitable for generating mmW-band signals directly, since, as the frequency increases, the capture range of their sampling operation is reduced rapidly, thereby hindering the reliable operation. To extend the capture range, a prescaler can be used after the VCO [2], but it increases the in-band PN and power consumption. Direct-mmW SSPLLs are limited even at suppressing out-of-band PN, since their PN skirt is determined by an mmW VCO that has a relatively low Q. To overcome the problems of analog SSPLLs, such as a large area and a PVT-sensitive loop gain, digital SSPLLs using ADCs to digitize the sampled voltage have been developed recently [3]. However, digital SSPLLs suffer from another problem in that, to reduce the quantization noise (Q-noise) and improve the overall IPN, they must use high-performance ADCs that concurrently have high-sampling frequencies, fine resolutions, and wide dynamic ranges. Thus, they demand high power and occupy larger area. -
dc.identifier.bibliographicCitation IEEE International Solid-State Circuits Conference, pp.258 - 260 -
dc.identifier.doi 10.1109/ISSCC.2019.8662532 -
dc.identifier.issn 0193-6530 -
dc.identifier.scopusid 2-s2.0-85063459231 -
dc.identifier.uri -
dc.identifier.url -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title A 76fs rms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization -
dc.type Conference Paper - 2019-02-17 -


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