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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)


Single-electron transistor based on a silicon-on-insulator quantum wire fabricated by a side-wall patterning method

DC Field Value Language Kim, DH ko Sung, SK ko Sim, JS ko Kim, Kyung Rok ko Lee, JD ko Park, BG ko Choi, BH ko Hwang, SW ko Ahn, D ko 2014-10-29T00:19:33Z - 2014-10-27 ko 2001-12 -
dc.identifier.citation APPLIED PHYSICS LETTERS, v.79, no.23, pp.3812 - 3814 ko
dc.identifier.issn 0003-6951 ko
dc.identifier.uri -
dc.identifier.uri ko
dc.description.abstract We propose and implement a promising fabrication technology for geometrically well-defined single-electron transistors based on a silicon-on-insulator quantum wire and side-wall depletion gates. The 30-nm-wide silicon quantum wire is defined by a combination of conventional photolithography and process technology, called a side-wall patterning method, and depletion gates for two tunnel junctions are formed by the doped polycrystalline silicon sidewall. The good uniformity of the wire suppresses unexpected potential barriers. The fabricated device shows clear single-electron tunneling phenomena by an electrostatically defined single island at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. ko
dc.description.statementofresponsibility open -
dc.language ENG ko
dc.publisher AMER INST PHYSICS ko
dc.subject COULOMB-BLOCKADE ko
dc.subject ROOM-TEMPERATURE ko
dc.subject VOLTAGE GAIN ko
dc.subject GATE ko
dc.subject DOT ko
dc.subject SWITCH ko
dc.title Single-electron transistor based on a silicon-on-insulator quantum wire fabricated by a side-wall patterning method ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-0035803208 ko
dc.identifier.wosid 000172362500022 ko
dc.type.rims ART ko
dc.description.wostc 25 *
dc.description.scopustc 26 * 2015-05-06 * 2014-10-27 *
dc.identifier.doi 10.1063/1.1421081 ko
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