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DC Field | Value | Language |
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dc.citation.conferencePlace | US | - |
dc.citation.endPage | 450 | - |
dc.citation.startPage | 448 | - |
dc.citation.title | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 | - |
dc.contributor.author | Kim, J. | - |
dc.contributor.author | Jo, Y. | - |
dc.contributor.author | Lim, Y. | - |
dc.contributor.author | Seong, T. | - |
dc.contributor.author | Park, H. | - |
dc.contributor.author | Yoo, S. | - |
dc.contributor.author | Lee, Y. | - |
dc.contributor.author | Choi, S. | - |
dc.contributor.author | Choi, J. | - |
dc.date.accessioned | 2024-01-31T22:07:55Z | - |
dc.date.available | 2024-01-31T22:07:55Z | - |
dc.date.created | 2021-04-19 | - |
dc.date.issued | 2021-02-13 | - |
dc.description.abstract | Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this high-gain operation of a sample-and-hold circuit (SH) also has a downside that makes it difficult to achieve a fractional resolution. This is because the quantization error (Q-error) due to the non-integer relationship between the reference frequency, fREF, and the VCO frequency, fVCO, easily makes sampling points fall outside the linear range of the SH. Thus, to have a fractional resolution, SSPLLs must have a dedicated method for cancelling the Q-error. The top left of Fig. 32.4.1 shows a time-domain Q-error cancellation (TD-QEC) that is currently popular [1]. As a digital-to-time converter (DTC) cancels the Q-error, the VCO output, SVCO, can be continuously sampled at high-KSH points in the steady state. However, a critical problem is that, since the DTC is located at the front, its thermal noise cannot be suppressed by KSH degrading the in-band phase noise (PN) of SSPLLs. In contrast, in reference-sampling PLLs (RSPLLs) [2], [3], the divided signal of the SVCO samples the reference clock, S_{REF.} However, they have a fundamental limit to achieve a low jitter since their KSH is much smaller than that of SSPLLs while the thermal noise of the DTC is still high. © 2021 IEEE. | - |
dc.identifier.bibliographicCitation | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021, pp.448 - 450 | - |
dc.identifier.doi | 10.1109/ISSCC42613.2021.9365815 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.scopusid | 2-s2.0-85102389865 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/77623 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2021-02-13 | - |
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