IC Level EMI Analysis using EMI Source Modeling

Abstract

Over the past decades, electronic applications have evolved for high speeding up the data process. Accordingly, the operating frequency of all electronic devices gets higher, and the systems have been integrated as much as possible to minimize the influence of parasitic components inside the system. Especially, in portable devices such as mobile phones, many of the chips including antennas are incorporated within a very short distance. In addition, with the development of 3D stacking packaging technology to improve the performance of each chip along with the form factor, the size of individual packages has become much larger. However, the radiated emission caused by high-speed signals and by the large structure size of each package has raised package-to-package electromagnetic interference (EMI) problems. The distances between components are also close enough to affect each other inside the integrated system. Interference between the components causes data distortion and even causes malfunction. Particularly, interference at the antenna by the adjacent components is fatal since it reduces the sensitivity of the receiving antenna inside the portable devices. Hence, many studies have previously been conducted to analyze the EMI from the integrated circuits (IC), but these research have several constraints or do not sufficient to predict exact EMI from the real operating incorporated IC. To overcome the limitations of previous research that for predicting the real IC EMI, the clarified EMI source information at the IC level is much desired. Thus, in this thesis, the novel modeling method of chip EMI source is proposed, and it is validated by comparing the simulation result and measurement result. In detail, an analysis of EMI from the package re-distribution layer (RDL) which is widely used in the newest mobile dynamic random-access memory (DRAM), LPDDR5, or others is discussed. In this research, the RDL is simply alternated into the simplified RDL structure using top metal in consideration of the wafer-level package process. After that, chip level EMI is analyzed for several conditions using a clarified EMI source model resulting in the proposed solution to reduce the chip EMI. Finally, the main contribution of this paper is addressed by dividing the chip EMI analysis into the chip functional element and the structural element, the chip EMI can be managed and predicted using the simple EMI source circuit model in the field simulator before manufacturing the chip package.