Measurement and Modeling of Noise Coupling and IC Failure due to System-level ESD Event

Abstract

Electrostatic discharge (ESD) is one of the most critical events on an electronic system. Due to a large discharge current with fast rise time, ESD event can cause not only system-level noises resulting in functional system failures but also permanent physical damages on an electronic device. To handle the ESD threat, accurate measurement and modeling of noise coupling and IC failure is the most important issue in system-level ESD event. In this thesis, the system-level ESD noise coupling was effectively modeled using the partial element equivalent circuit (PEEC) method or surface equivalence theorem for the first time. The PEEC method has several advantages in ESD simulations. First, the ESD generator circuit model and transmission line model can be incorporated with the PEEC method for efficient simulation. Second, the coupling contribution by the each ESD test geometry can be identified. Third, the small victim geometry can be separately handled from the entire ESD test geometry for efficient simulation. The simple victim geometries such as a conductor loop or two floating metal pieces were efficiently handled by ignoring the reverse effect from the victim structure to the large ESD aggressor structure. However, the reverse effect from the victim to aggressor should be considered in a signal trace victim geometry, since the interaction between the signal trace and the nearby aggressor metal plane could be significant in a signal propagation. So, a rigorous algorithm for efficient calculation without loss of accuracy by separating small victim signal traces from the large aggressor structures was derived using PEEC model decomposition. The calculated ESD-induced noise voltages were validated with the measurements and commercial full-wave solvers such as HFSS and CST. In the previous 3-D modeling of ESD generator, there was a limitation in modeling the direct field source from the relay inside ESD generator. Since the voltage collapse time across the internal relay is less than 100 ps, which is much faster than the rise time of ESD standard current, strong electromagnetic fields above 1 GHz can be radiated from the internal relay. In this thesis, The field sources of an ESD generator were efficiently modeled from the measured tangential magnetic fields in front of ESD generator using surface equivalence theorem. The extracted field sources were incorporated into a full-wave solver, and the system-level ESD noises due to electromagnetic fields radiated from an ESD generator were analyzed in a solid-state drive (SSD) storage system and compared with the measurement. The IC failure due to charged board event (CBE) was modeled and measured in this thesis. Commercial integrated circuits (ICs) were assembled on several practical PCB structures, and the discharging currents through individual pins of the IC induced by CBE were measured using shielded Rogowski coils. The overall CBE measurement setup was modeled and validated using circuit simulations. The structures of PCBs and a test ground plane were effectively modeled using a multilayered finite-difference method (MFDM). The ESD protection circuits in the IC were also modeled as behavioral circuit models. From the measurement and modeling of the CBE discharging currents at the IC pins, IC failure mechanisms were analyzed according to PCB structure, decoupling capacitor, and discharging points. Several strategies for IC protection against CBE risks were also obtained.