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dc.contributor.advisor Kang, Seokhyeong -
dc.contributor.author Lee, Jaemin -
dc.date.accessioned 2024-01-25T14:13:17Z -
dc.date.available 2024-01-25T14:13:17Z -
dc.date.issued 2017-08 -
dc.description.abstract The main goal of designing VLSI system is high performance with low energy consumption. Actually, to realize the human-related techniques, such as internet of things (IoTs) and wearable devices, efficient power management techniques are required. Near threshold computing (NTC) is one of the most well-known techniques which is proposed for the trade-off between energy consumption and performance improvement. With this technique, the solution would be selected by the lowest energy with highest performance.
However, NTC suffers a significant performance degradation, which is prone to timing errors. However, main goal of Integrated Circuit (IC) design is making the circuit to always operate correctly though worst-case condition. But, in order to make the circuit always work correctly, considerable area and power overheads may occur. As an alternative, better-than-worst-case (BTWC) design paradigm has been proposed. One of the main design of BTWC design includes error-resilient circuits which detect and correct timing errors, though they cause area and power overheads.
In this thesis, we propose various design methodologies which provide an optimal implementation of error-resilient circuits. Slack-based, sensitivity-based methodology and modified Quine-McCluskey (Q-M) algorithm have been exploited to earn the minimum set of error-resilient circuits without any loss of detection ability.
From sensitivity-based methodology, benchmark results show that the optimal designs reduces up to 46% monitoring area without compromising error detection ability of the initial error-resilient design.
From the Quine-McCluskey (Q-M) algorithm, benchmark results show that optimal design reduces up to 72% of flip-flops which are required to be changed to error-resilient circuits without compromising an error detection ability. In addition, more power and area reduction can be possible when reasonable underestimation of error detection ability is accepted. Monte-Carlo analysis validates that our proposed method is tolerant to process variation.
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dc.description.degree Master -
dc.description Department of Electrical Engineering -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/72179 -
dc.identifier.uri http://unist.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002380858 -
dc.language eng -
dc.publisher Ulsan National Institute of Science and Technology (UNIST) -
dc.rights.embargoReleaseTerms 9999-12-31 -
dc.title A Novel Methodology for Error-Resilient Circuits in Near-Threshold Computing -
dc.type Thesis -

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