Design of Automotive Communication Local Interconnect Network Transceiver for Physical Layer

Abstract

Car electronic system have grown consistently based on the trend change of the automotive component. For advanced application, there is considerable demand for high specification as substitute for mechanical devices. The electronic components are suitable for satisfaction of vendor and consumer requirements. There are various automotive communication for each application such as Controller Area Network(CAN), Local Area Network(LIN), FlexRay, Ethernet, etc. The automotive semiconductor is fundamental parts of the development trend for requirement trend based on vary communication. It has to endure artic condition for satisfaction of functional safety, because the automotive architecture must consider driver and passenger’s safety to protect harmful condition. AEC Q-100 is one of the safety standard for requirement of prime supplier such as GM, TOYOTA, Hyundai Motors, VOLVO, etc.. On the dissertation, it is main attention for implementation to satisfy standard of physical layer of LIN. Physical layer signal operating load can be described on International Standard Organization(ISO). There is under 20kbps input and output bit stream for communication, 5 us of overall system time constant and under 50% duty cycle. It targets Local Interconnect Network's physical layer given by ISO 17987-4. ECU generate digital bits stream, transmitter makes LIN bus signal which is driving application. Under 40% of battery voltage, regarded as logical ‘0’ which named Dominant state. Over 60% of battery voltage, regarded as logical ‘1’, which named Recessive state. LIN bus signal apply voltage to receiver block. Receiver transfer bus signal to output RXD pin for MCU. First implementation target complete signal data path to interconnection of input and output environment from ECU to application bus and application bus to ECU. It contains mode change option for resisting Electromagnetic Interference(EMI). Second and third design has advanced architecture for protection and satisfaction of standard. One targets the design for protection of inrush current based on current cell approach. It has technique which is reducing way of unit current cell mismatch from conventional data converter. The other one is delay control technique of input and output bit stream. ISO 17987 gives delay margin for physical layer, developer should satisfy the restriction. The mechanism can be controllable delay control from internal digital blocks.