Effect of Top-Gate Dielectric Deposition on the Performance of Indium Tin Oxide Transistors

Abstract

We report ultrathin (similar to 4 nm) channel indium tin oxide (ITO) transistors, comparing different precursors for atomic layer deposition (ALD) of the Al2O3 top-gate dielectric, and analyze the role of dielectric deposition on transistor performance and gate bias stress stability. Water-based ALD leads to very negative threshold voltage (V-T), with devices remaining in the on-state. In contrast, both ozone and O-2-plasma precursors yield devices that can turn off, but ozone-based ALD devices have less negative V-T shift at short channel lengths, and relatively more positive V-T at all channel lengths. We achieve maximum drive current, I-max approximate to 260 (mu)A/(mu)m at V-DS = 1 V, on/off current ratio of >10(10) (limited by the instrument's noise floor) for L approximate to 700 nm ozone-Al2O3 top-gated transistors. Across multiple devices, the effective mobility is similar to 42 cm(2)V(-1)s(-1) and contact resistance is similar to 376 Omega center dot mu m. The transistors also show good gate bias stability with normalized VT shift of +0.12 V(MV/cm)(-1) at gate stress field >3 MV/cm, a similar to 3x improvement vs. our previous reports of uncapped ITO transistors.