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DC Field | Value | Language |
---|---|---|
dc.citation.conferencePlace | BE | - |
dc.citation.conferencePlace | Leuven | - |
dc.citation.endPage | 300 | - |
dc.citation.startPage | 297 | - |
dc.citation.title | ESSCIRC 2004 | - |
dc.contributor.author | Ryoo, K.C. | - |
dc.contributor.author | Hwang, Y.N. | - |
dc.contributor.author | Lee, S.H. | - |
dc.contributor.author | Lee, S. | - |
dc.contributor.author | Ahn, S.J. | - |
dc.contributor.author | Song, Y.J. | - |
dc.contributor.author | Park, J.H. | - |
dc.contributor.author | Jeong, Changwook | - |
dc.contributor.author | Shin, J.M. | - |
dc.contributor.author | Jeong, W.C. | - |
dc.contributor.author | Koh, K.H. | - |
dc.contributor.author | Jeong, G.T. | - |
dc.contributor.author | Jeong, H.S. | - |
dc.contributor.author | Kim, K.N. | - |
dc.date.accessioned | 2023-12-20T05:38:53Z | - |
dc.date.available | 2023-12-20T05:38:53Z | - |
dc.date.created | 2022-04-06 | - |
dc.date.issued | 2004-09-21 | - |
dc.description.abstract | A 64Mb Phase Change Random Access Memory based on 0.1um technology is developed. We proposed several key factors such as BEC and GST cell size, contributing to stabilization of writing current for reversible cell transition. By reducing writing current to 1.1mA through such optimization, we have developed 64Mb PRAM. With memory functions and reliability tests, the feasibility for developing high-density 64Mb PRAM is presented. © 2004 IEEE. | - |
dc.identifier.bibliographicCitation | ESSCIRC 2004, pp.297 - 300 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.scopusid | 2-s2.0-20244387832 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/58541 | - |
dc.language | 영어 | - |
dc.publisher | ESSCIRC 2004 | - |
dc.title | Integration and cell characteristics for high - Density PRAM | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2004-09-21 | - |
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