dc.citation.conferencePlace |
KO |
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dc.citation.endPage |
114 |
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dc.citation.startPage |
111 |
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dc.citation.title |
IEEK 하계학술대회 |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.contributor.author |
Kim, Dae Hwan |
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dc.contributor.author |
Lee, Jong Duk |
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dc.contributor.author |
Park, Byung Gook |
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dc.date.accessioned |
2023-12-20T06:36:56Z |
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dc.date.available |
2023-12-20T06:36:56Z |
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dc.date.created |
2014-12-23 |
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dc.date.issued |
2000-06-01 |
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dc.description.abstract |
Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain. |
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dc.identifier.bibliographicCitation |
IEEK 하계학술대회, pp.111 - 114 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/52302 |
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dc.publisher |
IEEK |
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dc.title.alternative |
A study of Single Electron Logic Characterization Using a SPICE Macro-Modeling |
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dc.title |
단전자 트랜지스터로 구성된 논리 게이트 특성에 관한 연구 |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2000-06-01 |
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