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DC Field | Value | Language |
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dc.citation.endPage | 1670 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1659 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 39 | - |
dc.contributor.author | Pelard, C | - |
dc.contributor.author | Gebara, E | - |
dc.contributor.author | Kim, AJ | - |
dc.contributor.author | Vrazel, MG | - |
dc.contributor.author | Bien, Franklin | - |
dc.contributor.author | Hur, Y | - |
dc.contributor.author | Maeng, M | - |
dc.contributor.author | Chandramouli, S | - |
dc.contributor.author | Chun, C | - |
dc.contributor.author | Bajekal, S | - |
dc.contributor.author | Ralph, SE | - |
dc.contributor.author | Schmukler, B | - |
dc.contributor.author | Hietala, VM | - |
dc.contributor.author | Laskar, J | - |
dc.date.accessioned | 2023-12-22T10:42:19Z | - |
dc.date.available | 2023-12-22T10:42:19Z | - |
dc.date.created | 2014-06-09 | - |
dc.date.issued | 2004-10 | - |
dc.description.abstract | In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-mum GaAs HBTs and 0.18-mum CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 in of 500 MHz(.)km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-mum CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, no.10, pp.1659 - 1670 | - |
dc.identifier.doi | 10.1109/JSSC.2004.833569 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-5444242146 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/4897 | - |
dc.identifier.url | http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=5444242146 | - |
dc.identifier.wosid | 000224132500009 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scopus | - |
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