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Lee, Kyuho Jason
Intelligent Systems Lab.
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dc.citation.endPage 270 -
dc.citation.number 3 -
dc.citation.startPage 255 -
dc.citation.title JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE -
dc.citation.volume 20 -
dc.contributor.author Choi, Sungpill -
dc.contributor.author Lee, Kyuho Jason -
dc.contributor.author Kim, Youngwoo -
dc.contributor.author Yoo, Hoi-Jun -
dc.date.accessioned 2023-12-21T17:19:35Z -
dc.date.available 2023-12-21T17:19:35Z -
dc.date.created 2020-07-23 -
dc.date.issued 2020-06 -
dc.description.abstract The 3D hand gesture interface (HGI) for virtual reality and mixed reality on smart mobile devices is strongly dependent upon the robust depth-estimation with low latency and power consumption. However, the conventional depth-estimation hardware such as active depth sensors and stereo matching accelerators cannot realize the always-on and natural 3D HGI on mobile platform due to their large power consumption from active depth sensors and computations as well as the massive external memory bandwidth, respectively. To resolve the limit, we propose a depth-estimation processor that realizes the always-on and natural 3D HGI with algorithm and hardware co-optimization. The processor features: 1) shifter-based adaptive support weight aggregation that replaces complex floating-point operations with integer operations to reduce power and bandwidth by 92.2% and 69.1%; 2) line streaming 7-stage pipeline architecture with aggregation pipeline reordering optimization to realize 94% utilization and 43.9% memory reduction; and 3) shifting register-based pipeline buffer optimization to reduce 29.8% area. The proposed depth-estimation processor realizes a real-time 3D HGI with 9.52 ms of latency under QVGA stereo inputs. It achieves external memory bandwidth reduction to 18.93 MB/s with 15.56 mW power and 2.8 mm(2) area, which are 4.1x and 6.9x more efficient than state-of-the-arts [9, 10], respectively. -
dc.identifier.bibliographicCitation JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.20, no.3, pp.255 - 270 -
dc.identifier.doi 10.5573/JSTS.2020.20.3.255 -
dc.identifier.issn 1598-1657 -
dc.identifier.scopusid 2-s2.0-85087993490 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/47263 -
dc.identifier.url http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE09362851&language=ko_KR -
dc.identifier.wosid 000545341400005 -
dc.language 영어 -
dc.publisher IEEK PUBLICATION CENTER -
dc.title A 9.52 ms Latency, and Low-power Streaming Depth-estimation Processor with Shifter-based Pipelined Architecture for Smart Mobile Devices -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Engineering, Electrical & Electronic; Physics, Applied -
dc.relation.journalResearchArea Engineering; Physics -
dc.type.docType Article -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.description.journalRegisteredClass kci -
dc.subject.keywordAuthor Energy-efficient digital circuit -
dc.subject.keywordAuthor depth-estimation -
dc.subject.keywordAuthor stereo vision -
dc.subject.keywordAuthor low power -
dc.subject.keywordAuthor high throughput ASIC -
dc.subject.keywordAuthor image processing -
dc.subject.keywordAuthor memory-efficient design -

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