Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Quantum Wire

Abstract

The fabrication of single electron transistors (SET) with sidewall depletion gates on a silicon on insulator (SOI) quantum wire was proposed. A combination of conventional lithography and VLSI technology was used for the fabrication. The charge of electrically formed quantum dots was controlled by the control gate bias. The separation between the two sidewall gates was designed to be 37 nm and 185 nm respectively for the two SETs to incorporate high temperature operation and high voltage gain. The three-dimensional device simulation confirmed reliable operation of the Si based SET at 77K.