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DC Field | Value | Language |
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dc.citation.conferencePlace | JA | - |
dc.citation.conferencePlace | Tokyo | - |
dc.citation.endPage | 272 | - |
dc.citation.startPage | 267 | - |
dc.citation.title | Thirty-third International Symposium on Multiple-Valued Logic | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.contributor.author | Song, KW | - |
dc.contributor.author | Lee, SH | - |
dc.contributor.author | Kim, DH | - |
dc.contributor.author | Kyung, J | - |
dc.contributor.author | Baek, G | - |
dc.contributor.author | Lee, CA | - |
dc.contributor.author | Lee, JD | - |
dc.contributor.author | Park, BG | - |
dc.date.accessioned | 2023-12-20T06:06:58Z | - |
dc.date.available | 2023-12-20T06:06:58Z | - |
dc.date.created | 2014-12-23 | - |
dc.date.issued | 2003-05-16 | - |
dc.description.abstract | We propose a new technique to enhance the characteristics of CMOS/SET hybrid multi-valued logic (MVL) circuits in terms of their stability and performance. A complementary self-biasing method enables the SET/CMOS logic to operate perfectly well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical SET model, and it is confirmed that even SETs with a large Si island can be utilized efficiently in the multi-valued logic. We demonstrate a quantizer implemented by SETs with a 90-nm-long Si island on the basis of measured device characteristics and SPICE simulation, which shows high resolution and small linearity error characteristics. | - |
dc.identifier.bibliographicCitation | Thirty-third International Symposium on Multiple-Valued Logic, pp.267 - 272 | - |
dc.identifier.issn | 0195-623X | - |
dc.identifier.scopusid | 2-s2.0-0037481759 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/46894 | - |
dc.language | 영어 | - |
dc.publisher | Thirty-third International Symposium on Multiple-Valued Logic | - |
dc.title | Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2003-05-16 | - |
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