dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
New Orleans, LA |
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dc.citation.endPage |
196 |
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dc.citation.startPage |
193 |
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dc.citation.title |
IEEE International Symposium on Circuits and Systems |
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dc.contributor.author |
Kim, H |
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dc.contributor.author |
Bien, Franklin |
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dc.contributor.author |
Hur, Y |
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dc.contributor.author |
Chandramouli, S |
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dc.contributor.author |
Cha, J |
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dc.contributor.author |
Gebara, E |
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dc.contributor.author |
Laskar, J |
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dc.date.accessioned |
2023-12-20T05:06:12Z |
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dc.date.available |
2023-12-20T05:06:12Z |
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dc.date.created |
2014-12-23 |
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dc.date.issued |
2007-05-27 |
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dc.description.abstract |
In this paper, a BiCMOS equalizer using an active delay line structure for backplane communication is investigated. Equalization is achieved using a finite impulse response (FIR) filter. The filter is implemented using variable gain blocks and delay elements. The variable gain function is implemented using a Gilbert cell topology, modified for high-speed application. The delay line is implemented using active devices. The active delay line consumes less area than a passive L-C delay line, and has improved bandwidth as well as performance over process variation. The equalizer is implemented in a 0.25-mum BiCMOS technology. To the best our knowledge, it is the first BiCMOS equalizer using an active delay line approach. |
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dc.identifier.bibliographicCitation |
IEEE International Symposium on Circuits and Systems, pp.193 - 196 |
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dc.identifier.issn |
0271-4310 |
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dc.identifier.scopusid |
2-s2.0-34548836029 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46865 |
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dc.language |
영어 |
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dc.publisher |
IEEE CAS Society |
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dc.title |
A 0.25-um BiCMOS feed foward equalizer using active delay line for backplane communication |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2007-05-27 |
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