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Bien, Franklin
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dc.citation.conferencePlace US -
dc.citation.conferencePlace New Orleans, LA -
dc.citation.endPage 200 -
dc.citation.startPage 197 -
dc.citation.title IEEE International Symposium on Circuits and Systems - Bien, Franklin - Chandramouli, S - Kim, H - Gebara, E - Laskar, J - 2023-12-20T05:06:12Z - 2023-12-20T05:06:12Z - 2014-12-23 - 2007-05-27 -
dc.description.abstract In order for adaptive filter design to achieve optimum performance, the latency around the loop needs to be exactly designed for each targeted data rates. Due to unforeseen parasitic effects, latency has been major design issues for adaptive filters design with decision feedback
topologies. In this paper, a digitally controlled adjustable delay line IC is presented that can be tuned with 3-ps resolution with a modular-based digital-to-analog converter (DAC) design. The proposed adjustable delay line achieved wide bandwidth for 10-Gb/sec data throughput while demonstrating bit-error rate (BER) improvement for the given equalizer design over various band-limited channels. The proposed IC is implemented in a 0.18-um standard CMOS technology.
dc.identifier.bibliographicCitation IEEE International Symposium on Circuits and Systems, pp.197 - 200 -
dc.identifier.issn 0271-4310 -
dc.identifier.scopusid 2-s2.0-34548818488 -
dc.identifier.uri -
dc.language 영어 -
dc.publisher IEEE CAS Society -
dc.title Digitally controlled 10-Gb/s adjustable delay line for adaptive filter design in standard CMOS technology -
dc.type Conference Paper - 2007-05-27 -


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