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Bien, Franklin
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dc.citation.conferencePlace GE -
dc.citation.conferencePlace Technische Univ Munchen, M -
dc.citation.endPage 515 -
dc.citation.startPage 512 -
dc.citation.title European Solid-State Circuits Conference - Bien, Franklin - Chandramouli, Soumya - Gebara, Edward - Kim, Hyoungsoo - Laskar, Joy - 2023-12-20T04:40:13Z - 2023-12-20T04:40:13Z - 2014-12-23 - 2007-09-11 -
dc.description.abstract An unclocked analog decision-feedback equalizer (ADFE) is implemented in a 0.18-μm 40 GHz ft CMOS process to equalize legacy FR-4 backplane channels at 8-10-Gb/sec. The critical first feedback-loop latency requirement of the DFE is met by using a novel unclocked feedback topology and current-mode logic (CML) circuit building blocks. The circuit consists of a 4-tap linear analog feed-forward filter that cancels pre-cursor inter-symbol interference (ISI) to partially open the eye and a novel 1-tap analog tunable CML feedback filter that enables cancellation of the first post-cursor at 10-Gb/sec without the use of smaller process nodes or speculative techniques. The chip with pads occupies 1.04 mm2 and draws 240 mA DC current from a 1.8 V supply at a typical process corner. The ADFE is used to equalize 20 inches of FR-4 backplane traces at 8-Gb/sec and 10-Gb/sec. -
dc.identifier.bibliographicCitation European Solid-State Circuits Conference, pp.512 - 515 -
dc.identifier.doi 10.1109/ESSCIRC.2007.4430354 -
dc.identifier.scopusid 2-s2.0-44849099747 -
dc.identifier.uri -
dc.identifier.url -
dc.language 영어 -
dc.publisher IEEE; IEEE Electron Devices So -
dc.title A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-mu m CMOS -
dc.type Conference Paper - 2007-09-11 -


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