Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models

Abstract

Three dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise and cause additional IR-drop in power delivery network (PDN). In this work, we investigate and analyze the voltage noise in multiple layers 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then we propose multi-paired on-chip PDN structure for reducing voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately maximum 19% IR-drop reduction. In addition, layer dependency of 3D IC between the conventional and the proposed PDN models is analyzed.