Performance and Leakage Optimization with 22nm Bi-level FinFET

Abstract

In this paper, we analyze on- and off-current characteristic of the 22-nm Bi-level FinFET in which two different fin widths are formed. From the 3D Technology CAD (TCAD) simulations, we find out that the narrower the fin width the lower the leakage current. However, narrower fin width results in the reduced driving current for the triple-gate FinFET structure. We propose the optimal shape parameters of Bi-level FinFET such as the fin width and height of the narrower fin for providing better leakage current while keeping the required driving current of the nominal FinFET. Simulation results show that up to 4% speed up with 33% leakage current reduction by the optimal Bi-level FinFET compared to the nominal one.