dc.citation.conferencePlace |
KO |
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dc.citation.conferencePlace |
Ramada Plaza Jeju HotelJeju |
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dc.citation.endPage |
229 |
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dc.citation.startPage |
228 |
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dc.citation.title |
11th International SoC Design Conference, ISOCC 2014 |
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dc.contributor.author |
Ryu, Myunghwan |
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dc.contributor.author |
Kim, Youngmin |
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dc.date.accessioned |
2023-12-19T23:08:40Z |
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dc.date.available |
2023-12-19T23:08:40Z |
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dc.date.created |
2015-07-01 |
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dc.date.issued |
2014-11-05 |
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dc.description.abstract |
Increasing short channel effects (SCE) interrupt the further technology scaling in the CMOS transistors. Beyond 10 nm technology node, the gate-all-around (GAA) FET is considered as a promising solution for continuing the Moore's law. In this paper, we report the analysis of the double gate-all-around (DGAA) FET in terms of structural variations and the effect of the threshold voltage modulation by independently controlled inner gate. The impact of inner gate thickness and gate oxide thickness variations on the electrical characteristic of the DGAA FET are investigated. In addition, we propose the inner gate utilization to modulate the threshold voltage of the transistor for providing more design options. |
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dc.identifier.bibliographicCitation |
11th International SoC Design Conference, ISOCC 2014, pp.228 - 229 |
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dc.identifier.doi |
10.1109/ISOCC.2014.7087619 |
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dc.identifier.scopusid |
2-s2.0-84929429495 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46690 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/7087619 |
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dc.language |
영어 |
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dc.publisher |
11th International SoC Design Conference, ISOCC 2014 |
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dc.title |
Analysis of Structural Variation and Threshold Voltage Modulation in 10-nm Double Gate-All-Around (DGAA) Transistor |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2014-11-03 |
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