dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Santa Clara Convention CenterSanta Clara |
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dc.citation.endPage |
541 |
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dc.citation.startPage |
537 |
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dc.citation.title |
16th International Symposium on Quality Electronic Design, ISQED 2015 |
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dc.contributor.author |
Kim, Seungwon |
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dc.contributor.author |
Kang, Seokhyeong |
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dc.contributor.author |
Han, Ki Jin |
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dc.contributor.author |
Kim, Youngmin |
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dc.date.accessioned |
2023-12-19T22:40:42Z |
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dc.date.available |
2023-12-19T22:40:42Z |
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dc.date.created |
2015-07-01 |
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dc.date.issued |
2015-03-04 |
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dc.description.abstract |
Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC for a power gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power gating strategy that optimizes the inrush current profile, subject to the voltage-drop constraints. Our power gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve an average wake-up time reduction of 28% for all cases with our adaptive power gating method that exploits location (or layer) information of the aggressors in a 3D IC. |
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dc.identifier.bibliographicCitation |
16th International Symposium on Quality Electronic Design, ISQED 2015, pp.537 - 541 |
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dc.identifier.doi |
10.1109/ISQED.2015.7085483 |
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dc.identifier.issn |
1948-3287 |
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dc.identifier.scopusid |
2-s2.0-84944316538 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46669 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/7085483 |
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dc.language |
영어 |
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dc.publisher |
16th International Symposium on Quality Electronic Design, ISQED 2015 |
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dc.title |
Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2015-03-02 |
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