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김진국

Kim, Jingook
Integrated Circuit and Electromagnetic Compatibility Lab.
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dc.citation.conferencePlace GE -
dc.citation.conferencePlace International Congress Center DresdenDresden -
dc.citation.endPage 1314 -
dc.citation.startPage 1310 -
dc.citation.title 2015 Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe -
dc.contributor.author Park, Eunkyeong -
dc.contributor.author Kim, Jingook -
dc.contributor.author Lee, Jongjoo -
dc.contributor.author Park, Youngwoo -
dc.date.accessioned 2023-12-19T22:07:08Z -
dc.date.available 2023-12-19T22:07:08Z -
dc.date.created 2015-07-01 -
dc.date.issued 2015-08-18 -
dc.description.abstract The step response of a single ended output driver with silicon interposer channel is derived including the parasitics of ESD protection circuits. The probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated. With changing the frequency of supply voltage fluctuations, the effect of ESD parasitics on the output jitter is calculated and compared. -
dc.identifier.bibliographicCitation 2015 Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe, pp.1310 - 1314 -
dc.identifier.doi 10.1109/ISEMC.2015.7256360 -
dc.identifier.issn 10774076 -
dc.identifier.scopusid 2-s2.0-84953872919 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/46655 -
dc.identifier.url http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7256360 -
dc.language 영어 -
dc.publisher IEEE International Symposium on Electromagnetic Compatibility and EMC Europe -
dc.title Calculation of Power-Supply-Induced Jitter at a 3-D IC channel including ESD Protection Circuits -
dc.type Conference Paper -
dc.date.conferenceDate 2015-08-16 -

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