dc.citation.conferencePlace |
CH |
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dc.citation.conferencePlace |
Taipei |
- |
dc.citation.endPage |
831 |
- |
dc.citation.startPage |
825 |
- |
dc.citation.title |
Asia and South Pacific Design Automation Conference |
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dc.contributor.author |
Kahng, Andrew B. |
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dc.contributor.author |
Kang, Seokhyeong |
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dc.contributor.author |
Kumar, Rakesh |
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dc.contributor.author |
Sartori, John |
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dc.date.accessioned |
2023-12-20T03:39:59Z |
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dc.date.available |
2023-12-20T03:39:59Z |
- |
dc.date.created |
2015-07-01 |
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dc.date.issued |
2010-01-18 |
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dc.description.abstract |
Modern digital IC designs have a critical operating point, or “wall of slack”, that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a design-level approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to fail more gracefully. Compared with baseline designs, we achieve a maximum of 32.8% and an average of 12.5% power reduction at an error rate of 2%. The area overhead of our techniques, as evaluated through physical implementation (synthesis, placement and routing), is no more than 2.7%. |
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dc.identifier.bibliographicCitation |
Asia and South Pacific Design Automation Conference, pp.825 - 831 |
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dc.identifier.doi |
10.1109/ASPDAC.2010.5419690 |
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dc.identifier.scopusid |
2-s2.0-77951223419 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46632 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/5419690/ |
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dc.language |
영어 |
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dc.publisher |
2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 |
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dc.title |
Slack Redistribution for Graceful Degradation Under Voltage Overscaling |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2010-01-18 |
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