dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Anaheim, CA |
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dc.citation.endPage |
830 |
- |
dc.citation.startPage |
825 |
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dc.citation.title |
Design Automation Conference |
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dc.contributor.author |
Kahng, Andrew B |
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dc.contributor.author |
Kang, Seokhyeong |
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dc.contributor.author |
Kumar, Rakesh |
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dc.contributor.author |
Sartori, John |
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dc.date.accessioned |
2023-12-20T03:37:22Z |
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dc.date.available |
2023-12-20T03:37:22Z |
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dc.date.created |
2015-07-01 |
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dc.date.issued |
2010-06-15 |
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dc.description.abstract |
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings. |
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dc.identifier.bibliographicCitation |
Design Automation Conference, pp.825 - 830 |
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dc.identifier.doi |
10.1145/1837274.1837481 |
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dc.identifier.issn |
0738-100X |
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dc.identifier.scopusid |
2-s2.0-77956207873 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46631 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/5523631/ |
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dc.language |
영어 |
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dc.publisher |
47th Design Automation Conference, DAC '10 |
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dc.title |
Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2010-06-13 |
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