dc.citation.conferencePlace |
US |
- |
dc.citation.conferencePlace |
San Jose, CA |
- |
dc.citation.endPage |
239 |
- |
dc.citation.startPage |
233 |
- |
dc.citation.title |
IEEE/ACM International Conference on Computer- Aided Design |
- |
dc.contributor.author |
Hu, Jin |
- |
dc.contributor.author |
Kahnf, Andrew B. |
- |
dc.contributor.author |
Kang, Seokhyeong |
- |
dc.contributor.author |
Kim, Myung-Chul |
- |
dc.contributor.author |
Markov, Igor l |
- |
dc.date.accessioned |
2023-12-20T01:38:38Z |
- |
dc.date.available |
2023-12-20T01:38:38Z |
- |
dc.date.created |
2015-07-01 |
- |
dc.date.issued |
2012-11-06 |
- |
dc.description.abstract |
The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including Vt and Lg. Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest, we develop a metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints. Our solutions are evaluated using a rigorous protocol that computes circuit delay with Synopsys PrimeTime. Our implementation Trident outperforms the best-reported results on all but one of the ISPD 2012 benchmarks. Compared to the 2012 contest winner, we further reduce leakage power by an average of 43%. |
- |
dc.identifier.bibliographicCitation |
IEEE/ACM International Conference on Computer- Aided Design, pp.233 - 239 |
- |
dc.identifier.scopusid |
2-s2.0-84872316960 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46621 |
- |
dc.identifier.url |
http://ieeexplore.ieee.org/document/6386614 |
- |
dc.language |
영어 |
- |
dc.publisher |
IEEE |
- |
dc.title |
Sensitivity-Guided Metaheuristics for Accurate Discrete Gate Sizing |
- |
dc.type |
Conference Paper |
- |
dc.date.conferenceDate |
2012-11-05 |
- |