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dc.citation.conferencePlace JA -
dc.citation.title IEEE Symposium on VLSI Circuits -
dc.contributor.author Kim, Mina -
dc.contributor.author Choi, Seojin -
dc.contributor.author Choi, Jaehyouk -
dc.date.accessioned 2023-12-19T22:10:51Z -
dc.date.available 2023-12-19T22:10:51Z -
dc.date.created 2015-07-07 -
dc.date.issued 2015-06-18 -
dc.description.abstract This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than ± 4%. -
dc.identifier.bibliographicCitation IEEE Symposium on VLSI Circuits -
dc.identifier.doi 10.1109/VLSIC.2015.7231356 -
dc.identifier.scopusid 2-s2.0-84957885084 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/46598 -
dc.identifier.url http://ieeexplore.ieee.org/document/7231356/ -
dc.language 영어 -
dc.publisher IEEE -
dc.title A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells -
dc.type Conference Paper -
dc.date.conferenceDate 2015-06-17 -

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