Achieving Thermodynamic Limit of Subthreshold Slope by Inserting Pillar Structure in Nanoscale Schottky Barrier Field Effect Transistor

Abstract

As the device size shrinks continuously by scaling in the current Si CMOS technology, subthreshold slope which is related to device operation and leakage current goes from “bad” to “worse”. Especially, the subthreshold slope modulation that is one of the most interesting topics in metal/oxide/semiconductor field effect transistor (MOSFET) technology is quite difficult to achieve. We propose a new device structure, edge-over Schottky barrier field effect transistor (SBFET) which turns out to show subthreshold slope around the thermodynamic limit of Si MOSFET, 60 mV/dec. The edge-over SBFET has a unique pillar structure where the transistor channel is elongated by going over the edge of pillar. Hence, the edge-over SBFET has a much longer channel compared with the conventional planar MOSFET with the same transistor pitch. The interfaces between thin poly-silicon channel and Al electrodes (source and drain) form Schottky junctions with small Schottky barriers < 0.2 eV. We performed 2-dimensional TCAD modeling on an edge-over SBFET with horizontal channel length of 5.5 nm and ultra-thin channel thickness of 2.0 nm. The TCAD modeling predicts subthreshold slope of ~67.2 mV/dec and OFF-state current of ~13.5 nA . It is also noticed that subthreshold slope gets closer to the thermodynamic limit as the pillar height increases.