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DC Field | Value | Language |
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dc.citation.endPage | 2146 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 2134 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.citation.volume | 3 | - |
dc.contributor.author | Wang, Hanfeng | - |
dc.contributor.author | Pan, Siming | - |
dc.contributor.author | Kim, Jingook | - |
dc.contributor.author | Ruehli, Albert E. | - |
dc.contributor.author | Fan, Jun | - |
dc.date.accessioned | 2023-12-22T03:11:19Z | - |
dc.date.available | 2023-12-22T03:11:19Z | - |
dc.date.created | 2014-01-08 | - |
dc.date.issued | 2013-12 | - |
dc.description.abstract | In this paper, a new integral equation formulation for via structures is developed for the capacitance extraction between vias and planes. The formulation is initially developed for axially symmetric geometries and then extended to axially asymmetric geometries by changing the circular ring cells to arc cells. The extended method can be used to calculate the shared-antipad via structure, which is widely used in high-speed differential signal interconnects. In addition, the image theory is used to handle inhomogeneous media, and a new technique is given to reduce computational costs for via-to-plane structures based on properties of the capacitance-matrix elements. The proposed method is validated with a commercial finite element method-based tool for several practical via structures. The extracted capacitance is also incorporated into the physics-based via model and validated with full-wave simulations. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.12, pp.2134 - 2146 | - |
dc.identifier.doi | 10.1109/TCPMT.2013.2272323 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.scopusid | 2-s2.0-84891015188 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/3986 | - |
dc.identifier.url | http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84891015188 | - |
dc.identifier.wosid | 000328856700016 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Capacitance calculation for via structures using an integral equation method based on partial capacitance | - |
dc.type | Article | - |
dc.relation.journalWebOfScienceCategory | Engineering, Manufacturing; Engineering, Electrical & Electronic; Materials Science, Multidisciplinary | - |
dc.relation.journalResearchArea | Engineering; Materials Science | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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