dc.citation.conferencePlace |
KO |
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dc.citation.title |
2017 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD2017) |
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dc.contributor.author |
Jang, E-San |
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dc.contributor.author |
Shin, Sunhae |
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dc.contributor.author |
Jeong, Jae Won |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.date.accessioned |
2023-12-19T18:38:42Z |
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dc.date.available |
2023-12-19T18:38:42Z |
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dc.date.created |
2017-10-19 |
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dc.date.issued |
2017-07-03 |
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dc.description.abstract |
We propose a novel optimized design strategy by considering the correlated effects of high- gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical to lateral direction in 14-nm InAs n-FinFET and Ge p-FinFET with abrupt and high drain doping, the lateral GIDL is suppressed as 1/100 by high- spacer (e.g. TiO2) with high drive current of 1 mA/um and lower leakage current than 100 nA/um which works on lower operation voltage (VDD= 0.63V). DIBL is also suppressed below 100 mV/V by taking relatively lower- gate oxide (e.g. HfO2) than the high- spacer. |
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dc.identifier.bibliographicCitation |
2017 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD2017) |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/38777 |
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dc.language |
영어 |
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dc.publisher |
Electronics Society, The Institute of Electronics, Information and Communication Engineers of Japan (IEICE-ES) |
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dc.title |
Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2017-07-03 |
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